Due to a requirement for clock synchronization in wireless TimeDivisionDuplexing (TDD), 1588 clock synchronization based on a synchronous Ethernet gradually becomes mainstream clock synchronization technology in the communication industry.
In an existing network, factors such as an optical cable core error, an optical cable construction splicing error, an optical cable fault splicing error, a tail fiber error and the like may cause an asymmetric bidirectional length phenomenon in an optical fiber. This may lead to bidirectional asymmetry in a transmission delay. Existing network data shows that there is a substantial probability that optical fiber asymmetry will cause a time error of 100 ns or more. Thus, optical fiber asymmetry will be a major concern in constructing a clock synchronized network.
At present, in clock synchronized network deployment, methods used by an operator to handle asymmetry mainly includes: a 1588 test instrument, optical fiber switching, a single bidirectional fiber, automatic ring test, or the like. With a 1588 test instrument, point-by-point compensation is required in networking, which can barely be used in large-scale node networking. In switching using an optical switch, there is hardly any compatibility to an existing device, with possible damage to a service. With limited applicability, an automatic ring test allows performing error judgement only on an established time network. A single bidirectional fiber is problematic in terms of user customs and ease of use. For example, an existing single bidirectional fiber in general can only be used for transmission of about 20 km, but cannot be used for a transmission distance of 100 Km or more. All the methods are flawed when used in an existing network. Thus, automatic asymmetry compensation in 1588 clock synchronization has become a hard nut to crack in the industry. Lack of a solution thereof seriously impacts deployment of a wireless TDD clock synchronized network.
1588 clock synchronization in principle relies on bidirectional symmetry of a transmission delay of an intermediate path between two synchronous nodes. Thus, asymmetry will have a huge impact on 1588 clock synchronization. With bidirectional length asymmetry, no accurate clock synchronization can be implemented, leading to poor clock synchronization.